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I2C Protocol Subtleties – Part 1

I2C Protocol Subtleties – Part 1

This post is the initial in a series describing the additional ‘subtle’ factors of the I2C Protocol, at first developed by Philips.

Because you might be looking at this series, I’m assuming you already know what the I2C bus is, and you’re hunting to stay away from some discomfort when you have to have to use it in a undertaking. If so, you’ve got come to the right place. If not, I’ll be including some introductory I2C facts shortly at my web site.

Just so we’re crystal clear, this collection will not include coverage of the High-velocity mode, as this is significantly distinctive from the structure and actions of the regular 2-wire shared-bus implementation, and is also not that usually made use of. You will find loads of outstanding reference materials available on the Internet that handles this manner.

This is a quick listing of what will be coated in the rest of the sequence:

  • lacking Commence
  • lacking Prevent
  • Recurring Get started
  • lacking facts bits
  • missing ACK/NAK
  • details immediately after NAK
  • again-to-again mistakes
  • pullup resistors
  • bus repeaters
  • implementation working with a comprehensive-components TWI or I2C peripheral
  • implementation employing a USI peripheral
  • implementation working with a USART peripheral
  • SMBus discrepancies from I2C

Now, on to the good stuff!

For this report, we will concentration on the 3 styles of implementations you can obtain in styles now: total components, components/application blend, and comprehensive software (or ‘bit-bang’ as it is in some cases known as).

Numerous microcontrollers nowadays, even some minimal-conclusion products, include things like a thoroughly-hardware I2C peripheral. Atmel refers to theirs as TWI, Microchip phone calls theirs I2C other distributors use comparable naming. When using a absolutely-hardware tactic, it is actually tough to produce any form of bus mistake except if you misunderstand how the peripheral works or what a appropriate I2C bus sequence should really glimpse like. In standard, while, this technique necessitates the least in-depth understanding of the protocol alone.

The USI peripheral found in some Atmel equipment is a minimal-hardware design that relies upon on software package conversation to make it a comprehensive implementation. This multipurpose peripheral can actually be utilized for I2C, SPI and UART configurations, and is acceptable for small-finish devices the place including all 3 peripherals would be price-prohibitive. While it involves far more coding than a TWI or whole-components I2C peripheral, it is in some methods extra versatile. This approach requres a additional in-depth understanding of the protocol, as you are liable for transferring from just one point out to the following, and it is probable to go in the completely wrong course.

Last of all, applying a 100% program method calls for a complete knowledge of the I2C protocol. Almost each microcontroller vendor supplies software notes and code examples for generating an I2C Master machine applying a pure-application answer. Unlike a UART, I2C is a clocked (relatively than timed) protocol, so interruptions in the execution of the protocol are tolerated well, making it possible for interrupts to be serviced without having worry for losing knowledge. The highest pace of the software package-based answer is eventually identified by the CPU clock speed, and generally a Master implementation can simply attain the 400KHz amount.

A software program-based mostly implementation of a Slave device is considerably a lot more demanding. With out components help, the software have to keep an eye on both the SDA and the SCL lines concurrently in purchase to detect clock edges and know positively the condition of the SDA line prior to the increase or drop of SCL. Detection of a Start off or Quit issue will usually involve the use of interrupts, usually the software would need to have to be 100% eaten with monitoring SCL and SDA. Program-centered Slave implementations are likely to be CPU-sure, demanding numerous MIPS to accomplish even 100KHz procedure. For that reason, accurate program-only Slave implementations may well not even exist for some microcontroller families, and other individuals may perhaps not be capable of achieving full 100KHz bus pace.

With this components and application foundation acquiring been laid, we will dive further into the protocol alone in our following short article. Many thanks for looking through!

(Copyright 2010 Robert G. Fries)